On Thursday 26 March 2009 14:15:26 Kendrick Hamilton wrote: > When writing the process activation list for a flip-flop I usually only > include the clock and asynchronous reset. By having all the other > signals in there you may get latches instead of flip-flops. Try changing > > Mutex_states : process(clk, reset, CurrentState, HatfieldReq, McCoyReq) > to > Mutex_states: process(clk, reset)
The original code is over specified, but only clk and reset actually affect the process. So having the other signals listed is not good, but doesn't do anything but make it execute slower (and it's more confusing to a human reader). > Also, since I use Xilinx FPGAs I usually use synchronous resets, as that > is what the FPGA logic actually has. An asynchronous reset add more > logic. Kendrick (As a totally off-topic note, Xilinx FPGAs actually have both primitive synchronous and asynchronous reset capability on their FFs, controlled by a per-slice configuration bit. Using one or the other will not affect resource usage unless you try to use both at the same time.) -- Wesley J. Landaker <[email protected]> <xmpp:[email protected]> OpenPGP FP: 4135 2A3B 4726 ACC5 9094 0097 F0A9 8A4C 4CD6 E3D2
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