The problem might be a VHDL coding style / digital logic design issue.
Without spending any time guessing at the intentions of the original
model, I did a quick code/logic clean-up...included below FWIW.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Mutex is
port (
clk : in std_logic;
reset : in std_logic;
HatfieldReq : in std_logic;
McCoyReq : in std_logic;
StateOut : out std_logic_vector(3 downto 0);
NextStateOut : out std_logic_vector(3 downto 0);
HatfieldGrant : out std_logic;
McCoyGrant : out std_logic);
end Mutex;
architecture Behavioral of Mutex is
type states is
(Check_Req, Issue_HatfieldGrant, Wait4_HatfieldReqDone,
Issue_McCoyGrant, Wait4_McCoyReqDone);
signal NextState : states;
signal CurrentState : states;
signal StateOut_int, NextStateOut_int : std_logic_vector(3 downto 0);
signal HatfieldGrant_int, McCoyGrant_int : std_logic;
begin
NextStateLogic : process (CurrentState, HatfieldReq, McCoyReq)
begin
case CurrentState is
when Check_Req =>
StateOut_int <= x"1";
HatfieldGrant_int <= '0';
McCoyGrant_int <= '0';
if (HatfieldReq = '1') then
NextState <= Issue_HatfieldGrant;
NextStateOut_int <= x"2";
elsif (McCoyReq = '1') then
NextState <= Issue_McCoyGrant;
NextStateOut_int <= x"4";
else
NextState <= Check_Req;
NextStateOut_int <= x"1";
end if;
-- Grant ARM access to resource
when Issue_HatfieldGrant =>
StateOut_int <= x"2";
NextStateOut_int <= x"3";
HatfieldGrant_int <= '1';
McCoyGrant_int <= '0';
NextState <= Wait4_HatfieldReqDone;
when Wait4_HatfieldReqDone =>
StateOut_int <= x"3";
McCoyGrant_int <= '0';
if (HatfieldReq = '1') then
HatfieldGrant_int <= '1'; -- I am guessing this is the
desired behavior.
NextState <= Wait4_HatfieldReqDone;
NextStateOut_int <= x"3";
else
HatfieldGrant_int <= '0';
NextState <= Check_Req;
NextStateOut_int <= x"1";
end if;
-- End of ARM access
-- Grant PC access to resource
when Issue_McCoyGrant =>
StateOut_int <= x"4";
HatfieldGrant_int <= '0';
McCoyGrant_int <= '1';
NextState <= Wait4_McCoyReqDone;
NextStateOut_int <= x"5";
when Wait4_McCoyReqDone =>
StateOut_int <= x"5";
HatfieldGrant_int <= '0'; -- I am guessing this is the
desired behavior.
if (McCoyReq = '1') then
McCoyGrant_int <= '1';
NextState <= Wait4_McCoyReqDone;
NextStateOut_int <= x"5";
else
McCoyGrant_int <= '0'; -- I am guessing this is the
desired behavior.
NextState <= Check_Req;
NextStateOut_int <= x"1";
end if;
-- End of PC access
when others => -- I am guessing this is the desired behavior.
StateOut_int <= x"F";
NextStateOut_int <= x"1";
HatfieldGrant_int <= '0';
McCoyGrant_int <= '0';
NextState <= Check_Req;
end case;
end process NextStateLogic;
Mutex_states : process(clk, reset, NextState, HatfieldGrant_int,
McCoyGrant_int, StateOut_int, NextStateOut_int)
begin
if (reset = '1') then
CurrentState <= Check_Req;
HatfieldGrant <= '0';
McCoyGrant <= '0';
StateOut <= x"0";
NextStateOut <= x"1";
elsif rising_edge(clk) then
CurrentState <= NextState;
HatfieldGrant <= HatfieldGrant_int;
McCoyGrant <= McCoyGrant_int;
StateOut <= StateOut_int;
NextStateOut <= NextStateOut_int;
end if;
end process Mutex_states;
end Behavioral;
2009/3/26 Wesley J. Landaker <[email protected]>:
> On Thursday 26 March 2009 12:59:54 Steve Franks wrote:
>> Hi,
>>
>> I'm seeing something I can't understand - bug?
>>
>> Look at test3, subtest3. Note how we pingpong between states 3 & 5.
>> Somehow that's either a
>> problem, or I'm missing something obvious....
>
> When I try your example with GHDL 0.27+svn110 on Debian, it seems to work
> how I'd expect from a quick glance at the code. Attached is a snapshot from
> gtkwave.
>
> --
> Wesley J. Landaker <[email protected]> <xmpp:[email protected]>
> OpenPGP FP: 4135 2A3B 4726 ACC5 9094 0097 F0A9 8A4C 4CD6 E3D2
>
> _______________________________________________
> Ghdl-discuss mailing list
> [email protected]
> https://mail.gna.org/listinfo/ghdl-discuss
>
>
_______________________________________________
Ghdl-discuss mailing list
[email protected]
https://mail.gna.org/listinfo/ghdl-discuss
