Here are three small test cases for the problems encountered in porting
the processor to GHDL:
Dimensionless vector constants
------------------------------
Test case v1.vhd:
library ieee;
use ieee.std_logic_1164.all;
entity e is
port (
clk : in std_logic;
resetn : in std_logic
);
end e;
architecture a of e is
constant S0 : std_logic_vector := "10";
constant S1 : std_logic_vector := "11";
constant S2 : std_logic_vector := "00";
constant S3 : std_logic_vector := "01";
--constant S0 : std_logic_vector (1 downto 0) := "10";
--constant S1 : std_logic_vector (1 downto 0) := "11";
--constant S2 : std_logic_vector (1 downto 0) := "00";
--constant S3 : std_logic_vector (1 downto 0) := "01";
signal state : std_logic_vector (1 downto 0);
begin
p1: process (clk, resetn)
begin
if (resetn = '0') then
state <= S0;
elsif (clk'event and clk = '1') then
case state is
when S0 =>
state <= S1;
when S1 =>
state <= S2;
when S2 =>
state <= S3;
when others => -- S3
state <= S0;
end case;
end if;
end process p1;
end a;
ghdl -a --ieee=synopsys --workdir=workdir v1.vhd
Results in:
v1.vhd:35:15: choice must be locally static expression
v1.vhd:38:15: choice must be locally static expression
v1.vhd:41:15: choice must be locally static expression
ghdl: compilation error
The commented-out alternative code avoids the problem.
Ambiguous integer operands to mod
---------------------------------
Test case v2.vhd:
library ieee;
use ieee.std_logic_1164.all;
package p_pack is
procedure p1 (s : in std_logic_vector);
end p_pack;
package body p_pack is
procedure p1 (s : in std_logic_vector) is
begin
case s'length mod 4 is
--case integer'(s'length) mod 4 is
when 1 => null;
when 2 => null;
when 3 => null;
when others => null;
end case;
end procedure p1;
end p_pack;
ghdl -a --ieee=synopsys --workdir=workdir v2.vhd
results in:
v2.vhd:13:21: can't resolve overload for operator "mod"
v2.vhd:13:21: possible interpretations are:
*std_standard*:1:1: integer
*std_standard*:1:1: UNIVERSAL_INTEGER
ghdl: compilation error
The commented-out alternative code avoids the problem.
hread failure for vector of length 8
------------------------------------
library std;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
entity e is
end entity e;
architecture a of e is
begin
p: process
file f : text open READ_MODE is "f_data";
variable inline1 : line;
variable inline2 : line;
variable outline : line;
variable b4 : std_logic_vector ( 3 downto 0);
variable b8 : std_logic_vector ( 7 downto 0);
variable b12 : std_logic_vector (11 downto 0);
variable b16 : std_logic_vector (15 downto 0);
variable b32 : std_logic_vector (31 downto 0);
begin
while not endfile (f) loop
write (outline, string'("Attempt read ..."));
writeline (output, outline);
readline (f, inline1);
readline (f, inline2);
if inline1 /= null and inline2 /= null then
write (outline, inline1.all & " = ");
if inline1.all = "Read 32 bits" then
hread(inline2, b32);
hwrite (outline, b32);
elsif inline1.all = "Read 16 bits" then
hread(inline2, b16);
hwrite (outline, b16);
elsif inline1.all = "Read 12 bits" then
hread(inline2, b12);
hwrite (outline, b12);
elsif inline1.all = "Read 8 bits" then
hread(inline2, b8);
hwrite (outline, b8);
elsif inline1.all = "Read 4 bits" then
hread(inline2, b4);
hwrite (outline, b4);
else
report "Could not interpret: " & inline1.all
severity failure;
end if;
writeline (output, outline);
end if;
end loop;
wait;
end process p;
end architecture a;
Data file f_data:
Read 32 bits
abcdef01
Read 16 bits
2345
Read 12 bits
678
Read 8 bits
9c
Read 4 bits
f
ghdl -a --ieee=synopsys --workdir=workdir v3.vhd
ghdl -e --ieee=synopsys --workdir=workdir e
./e
Results in:
Attempt read ...
Read 32 bits = ABCDEF01
Attempt read ...
Read 16 bits = 2345
Attempt read ...
Read 12 bits = 678
Attempt read ...
./e:error: bound check failure at ../../../src/std/textio_body.v93:1311
./e:error: simulation failed
This can be avoided by changing line 8 of the data from "9c" to "9cK".
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