From: Kelvin Gardiner <[email protected]> Subject: [Ghdl-discuss] Dumping local signals / variables to VCD file Date: Tue, 17 Nov 2009 11:53:17 +0000
> I've just started to use gHDL. I have a design with local variables > inside a process block. After running a simulation these signals are not > in the VCD file. How can I get gHDL to dump all signals / variables in > the design? The VCD format was defined many years ago in the Cadence (or even Gateway) Verilog-XL manual. Hence it only supports Verilog style wire, reg, etc. Not even enumerated types are supported by VCD. Hence you're better off using the native dump format of ghdl. Run your simulation with ghdl -r my_tb --wave=my_tb.ghw. You can then use gtkwave to open ghw files. Unfortunately I don't know if there is a way to log variables in the ghw file, but you will at least see enums. Petter _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
