Kelvin Gardiner escribió: > Hi, > > I've just started to use gHDL. I have a design with local variables > inside a process block. After running a simulation these signals are not > in the VCD file. How can I get gHDL to dump all signals / variables in > the design? > Dumping variables is a paradox: variables can change many times for the same time, how can you draw it in a timeline? You could only dump the "last" value for the variable. IMHO accessing variables is nice for simulators where you can "step" in the HDL code.
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