On Fri, Jan 22, 2010 at 4:29 PM, Bill Toner <[email protected]> wrote: > In pondering how one might approach a mixed-language simulation with FOSS > tools, I recently noticed that Icarus can compile the verilog input and > export it to VHDL. Has anyone tried to bring this translated VHDL from > verilog into a GHDL simulation? How well would this work? Is it usable, or > more of an automated beginning to a translation which will require manual > effort as well to make that VHDL usable?
FWIW, I've succesfully done what I've called (in my master thesis) heterogenous verification with FOSS tools [and COTS tools]. (I've developed a framework where you can verify a design made of components simulated using either MATLAB, ModelSim, GHDL and OSCI sim. I make these simulators communicate via TAO's CORBA implementation. See [1] and [2] for more details.) In terms of FOSS tools-only, I did verification using the Open SystemC Initiative simulator and GHDL. While we had different objectives and used different approaches, I'm not the only one who did "heterogenous" verification using GHDL and OSCI sim.; Richard Maciel also did. In both cases, with GHDL, we used VHPI. -Pascal [1] http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4683393&tag=1 [2] http://organact.mine.nu/dokuwiki/_media/mesetudes:mnrc08.pdf?id=mesetudes&cache=cache -- Homepage (http://organact.mine.nu) Debian GNU/Linux (http://www.debian.org) LACIME: École de technologie supérieure (http://lacime.etsmtl.ca) _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
