On Tue, 10 Aug 2010 21:06:46 +0530, ejoftiduttu <ejoftidu...@gmail.com> wrote: > Dear friends > I tried to do a simple program based on counter. > > This is the program > > process(clock, count, clear) > begin > if clear = '1' then > Pre_Q <= Pre_Q + Pre_Q; ???? clear should do Pre_Q <= (others=>'0');
> elsif (clock='1' and clock'event) then > if count = '1' then > Pre_Q <= Pre_Q + 1; > end if; > end if; > end process; > it's explained there : http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#integer_bit_vector in short : cast to the "unsigned" type and cast the result back to std_ulogic_vector Pre_Q <= std_logic_vector(unsigned(Pre_Q) + 1); or something like that. yg _______________________________________________ Ghdl-discuss mailing list Ghdl-discuss@gna.org https://mail.gna.org/listinfo/ghdl-discuss
