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>
> When i tried to analyse it using ghdl i'm getting the error msg like this
>
>
> [ejo...@linuxpoint ~]$ ghdl -a counter.vhdl
> counter.vhdl:29:27: no function declarations for operator "+"
> counter.vhdl:32:31: no function declarations for operator "+"
> ghdl: compilation error
> [ejo...@linuxpoint ~]$
>
> Please help me
>
> With regards
> Ejofti.
>
always use unsigned or signed type as internal signals when you need to
do arithmetic operations (CHANGE 1) , convert to/from std_logic_vector
to/from ports to be compliant with backend tools. (CHANGE 2)
On your code this give:
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is
generic(n: natural :=2);
port( clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(n-1 downto 0)
);
end counter;
architecture behv of counter is
signal Pre_Q: unsigned(n-1 downto 0); -- <<<< CHANGE 1 HERE
begin
process(clock, count, clear)
begin
if clear = '1' then
Pre_Q <= Pre_Q + Pre_Q;
elsif (clock='1' and clock'event) then
if count = '1' then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;
Q <= std_logic_vector(Pre_Q); -- <<<< CHANGE 2 HERE
end behv;
- ---------
This technique is more readable than
Pre_Q <= std_logic_vector(unsigned(Pre_Q) + 1);
but you can use this style when you work directly on input and output ports.
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