Nice work! Sounds really good! Do you still get a significant speedup for std_logic_ vector of other more arbitrary lengths - e.g. 13 or 17 or 31?
What about vectors longer than 32 bits? Would you still get a dramatic speed-up on a 32 bit machine? How does your new source code handle the odd 'U' or 'Z' in amongst '1' s and '0's? Thanks for your efforts and announcing your discovery! Long LIve Open Source! -----Original Message----- From: [email protected] Reply-to: GHDL discuss list <[email protected]> To: GHDL discuss list <[email protected]> Subject: Re: [Ghdl-discuss] 400x speedup in behavioural simulation Date: Mon, 14 Feb 2011 18:01:49 +0100 On Mon, 14 Feb 2011 17:48:59 +0100, Lluís Batlle i Rossell <[email protected]> wrote: >> I just put the sources at http://ygdes.com/GHDL/int_bool >> run sha-1.sh after editing the top of sha-1.vhdl >> to suite one of the 4 options. > Also additions could be done that way, isn't it? they are done already :-) +, -, *, /, exp and mod are available. I added and/or/not/nand/nor/xor/xnor, shift and rotate. The microbenchmark is a SHA-1 kernel that makes use of most of these with 32-bit variables : no wonder the speedup is that good. In practical cases, I expect 50 to 200x speedup and still be able to synthesize the VHDL code by switching the libraries :-) Not everything is solved however. array subscripts must be handled in some way, through shifts for the integer version, and normal subscripts for the std_ulogic version, plus other gotchas... but i'm getting there :-D YG _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
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