You can use global variable 2011/2/18, Christophe Clienti <[email protected]>: > I need to access to internal signals of a design under test in a vhdl > testbench. The tested design instanciates multiple entities and I don't want > to change them by adding a port to monitor desired signals. > Is there some possibilities to do that (in vhdl or in a c program) ? > > Christophe >
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