Hi, With at least the versions 0.31 and 0.32 of GHDL, I have some VHDL designs for which simulation is extremely slow. By "extremely", I mean 1 cycle per minute. The same VHDL code is simulated at at least 1000 cycles/s with Xilinx's simulator.
This situation is rare but fully reproducible. I wanted to find how the lastest GHDL version would perform so I recompiled GHDL from source yesterday evening using Archlinux package : https://aur.archlinux.org/packages/ghdl/ Attached is the VHDL code of one application for which the extreme slowdown happens. I may produce other applications later. Note: the VHDL code is generated by an HLS tool so don't expect to understand what happens. Here is what I suspect about what happens: the VHDL design can contain combinatorial loops, so the simulator has to compute all the "delta" steps. But in that case I don't understand why Xilinx's simulator simulates the same code at 1000 cycles/s. How does GHDL behave when there is a combinatorial loop that does not stabilizes between 2 clock edges? Can I expect a warning to be printed? Could this be a bug in the executabe generated by GHDL? Regards, Adrien
vhdl.tar.gz
Description: application/compressed-tar
_______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
