On 08/11/14 13:41, Adrien Prost-Boucle wrote:
Hi,
With at least the versions 0.31 and 0.32 of GHDL, I have some VHDL
designs for which simulation is extremely slow. By "extremely", I mean 1
cycle per minute. The same VHDL code is simulated at at least 1000
cycles/s with Xilinx's simulator.
Hello,
some news. This is still work in progress, but currently:
$ time ./tb
...
INFO clock cycle 7302
INFO clock cycle 7303
INFO Output nb 149 at cycle 7304 (check OK) Obtained
00000000000000000000000000111010
INFO Last output vector read at cycle 7304
tb.vhd:305:48:@73045ns:(report note): INFO Stopping simulation.
INFO clock cycle 7304
INFO clock cycle 7305
INFO clock cycle 7306
INFO clock cycle 7307
real 0m4.980s
user 0m4.901s
sys 0m0.068s
There was indeed room for improvement.
Tristan.
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