Hello Adrien, can you post a complete example or upload it to GIST (https://gist.github.com/)? Are you using switching different implementations or entity/architectures with that if..generate?
Regards
Patrick
-----------------------------------
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-----Original Message-----
From: Ghdl-discuss [mailto:ghdl-discuss-boun...@gna.org] On Behalf Of Adrien
Prost-Boucle
Sent: Friday, December 04, 2015 12:06 AM
To: GHDL discuss list <ghdl-discuss@gna.org>
Subject: [Ghdl-discuss] Questions: error in if-generate with false condition
Hi,
I want to instantiate a component inside an if-generate.
Depending on which if-generate statement has the condition evaluated as true,
some ports may not match the component...
if false generate
component comp is
port(
a : in std_logic;
b : out std_logic
);
begin
i_comp: comp
port map(
a => a,
b => b
);
end generate;
If the current entity for comp does not have the same ports, like one of them
is missing in instantiation or a name is different, ghdl fails.
However the condition is false so this kind of error inside this generate
statement may be common.
For example, have a testbench that can drive a design with or without some
debug ports or optional scan chain.
Would it be possible to disable some errors in false if-generate statements?
Regards,
Adrien
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