Hi, If it's not compatible with the LRM then indeed using configurations should be the solution, even if it involves some more code. Thanks for the suggestion.
Regards, Adrien On Fri, 2015-12-04 at 09:13 +0100, tging...@free.fr wrote: > Hello, > > > I want to instantiate a component inside an if-generate. > > Depending on which if-generate statement has the condition > > evaluated > > as > > true, some ports may not match the component... > > > > if false generate > > > > component comp is > > port( > > a : in std_logic; > > b : out std_logic > > ); > > > > begin > > > > i_comp: comp > > port map( > > a => a, > > b => b > > ); > > > > end generate; > > > > If the current entity for comp does not have the same ports, like > > one > > of them is missing in instantiation or a name is different, ghdl > > fails. > > However the condition is false so this kind of error inside this > > generate statement may be common. > > For example, have a testbench that can drive a design with or > > without > > some debug ports or optional scan chain. > > > > Would it be possible to disable some errors in false if-generate > > statements? > > As far as I know, your suggestion is not compatible with the VHDL > LRM. > You should use configurations to avoid this issue: do not bind the > component. > > Regards, > Tristan. > _______________________________________________ Ghdl-discuss mailing list Ghdl-discuss@gna.org https://mail.gna.org/listinfo/ghdl-discuss
