Hello Adrien, Can you give some information on your used GHDL installation? - version number or source code checkout date - backend: gcc, llvm, mcode
Are you exporting the simulation results as a waveform dump file? E.g. vcd,
fst, ghw, ...
=> This has a high performance impact, caused by string operations and file I/O
What is the used VHDL version?
Are you running xSim in multi-threaded mode?
-mt on|off|2...n (it's enabled by default)
Regards
Patrick
-----------------------------------
Wissenschaftliche Hilfskraft
Technische Universität Dresden
Fakultät Informatik
Institut für Technische Informatik
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-----Original Message-----
From: Ghdl-discuss [mailto:ghdl-discuss-boun...@gna.org] On Behalf Of Adrien
Prost-Boucle
Sent: Wednesday, March 09, 2016 9:38 PM
To: GHDL discuss list <ghdl-discuss@gna.org>
Subject: [Ghdl-discuss] Huge simulation speed slowdown
Hi,
I have a VHDL design that GHDL simulates at a speed of only one or 2 clock
cycles per second. The same design, same VHDL files, is simulated by Xilinx
Vivado 2015.3 at a speed of 400 clock cycles per second.
For all other designs I have and/or generate, GHDL is always noticeably faster
that Vivado, so I think my current app exhibits a GHDL behaviour that at least
could be improved.
Note that the attached VHDL was generated by a HLS tool so it's not easy to
read... and unfortunately I can't reduce the VHDL code to something simpler
that exhibits the slowdown.
The top-level entity is the testbench entity "tb". The simulation is supposed
to stop after around 550k clock cycles.
Good evening,
Adrien
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