Hello Adrien, Please compare it to the LLVM backend, because LLVM has several good optimization options. I just wanted to make sure that your GHDL is an almost up-to-date 0.34dev built and not 0.31 or so :).
I think xSim can use multi-threading in simulation, too. Otherwise I cannot explain, why my current project suffers from race conditions while using shared variables .... There is also an --O2 command line switch on xelab.exe => it's internally using gcc (from MinGW). Maybe you want to try an unoptimized xSim run ... Btw. Vivado comes with some nice libraries and tools like MinGW, LLVM (clang), GnuPlot, Git, ... I don't know if xSim uses LLVM, too. I could imaging that your code produces many delta cycles. There is a way to print out every cycle and delta-cycle. The option is called --disp-time => http://ghdl.readthedocs.org/en/latest/Simulation_and_runtime.html#cmdoption--disp-time I could imaging having <20 delta cycles per real simulation step would be normal. You could launch your simulation with this option and pipe the endless list of outputs into a logfile and abort it after 1 minute or so. A short view into the file or a short script should show how many delta-cycles are needed per simulation step. Regards Patrick ----------------------------------- Wissenschaftliche Hilfskraft Technische Universität Dresden Fakultät Informatik Institut für Technische Informatik Lehrstuhl VLSI-Entwurfssysteme, Diagnostik und Architektur 01062 Dresden Tel.: +49 351 463-38451 Fax: +49 351 463-38324 Raum: APB-1020 E-Mail: patrick.lehm...@tu-dresden.de WWW: http://vlsi-eda.inf.tu-dresden.de -----Original Message----- From: Ghdl-discuss [mailto:ghdl-discuss-boun...@gna.org] On Behalf Of Adrien Prost-Boucle Sent: Thursday, March 10, 2016 12:12 AM To: ghdl-discuss@gna.org Subject: Re: [Ghdl-discuss] Huge simulation speed slowdown Hi Patrick, Good questions, sorry for having forgotten that. I used both gcc and mcode backends. mcode pulled from git this afternoon, gcc older by a few weeks. I don't have the exact commit IDs right now, that's in the lab. I can provide them if needed and test with latest gcc and llvm backends too. I used no wave export. I used xSim with default settings. However I noticed the CPU usage barely reached 100%, that's one CPU. But multithreading is used only for compilation if I remember correctly. Just in case, in the past I mentioned a similar slowdown situation: https://mail.gna.org/public/ghdl-discuss/2014-11/msg00064.html Of course the present issue may be completely unrelated. Adrien On Wed, 2016-03-09 at 21:50 +0000, Lehmann, Patrick wrote: > Hello Adrien, > > Can you give some information on your used GHDL installation? > - version number or source code checkout date > - backend: gcc, llvm, mcode > > Are you exporting the simulation results as a waveform dump file? E.g. vcd, > fst, ghw, ... > => This has a high performance impact, caused by string operations and file > I/O > > What is the used VHDL version? > > Are you running xSim in multi-threaded mode? > -mt on|off|2...n (it's enabled by default) > > Regards > Patrick > > ----------------------------------- > Wissenschaftliche Hilfskraft > > Technische Universität Dresden > Fakultät Informatik > Institut für Technische Informatik > Lehrstuhl VLSI-Entwurfssysteme, Diagnostik und Architektur > 01062 Dresden > Tel.: +49 351 463-38451 > Fax: +49 351 463-38324 > Raum: APB-1020 > E-Mail: patrick.lehm...@tu-dresden.de > WWW: http://vlsi-eda.inf.tu-dresden.de > > -----Original Message----- > From: Ghdl-discuss [mailto:ghdl-discuss-boun...@gna.org] On Behalf Of Adrien > Prost-Boucle > Sent: Wednesday, March 09, 2016 9:38 PM > To: GHDL discuss list <ghdl-discuss@gna.org> > Subject: [Ghdl-discuss] Huge simulation speed slowdown > > Hi, > > I have a VHDL design that GHDL simulates at a speed of only one or 2 clock > cycles per second. The same design, same VHDL files, is simulated by Xilinx > Vivado 2015.3 at a speed of 400 clock cycles per second. > > For all other designs I have and/or generate, GHDL is always noticeably > faster that Vivado, so I think my current app exhibits a GHDL behaviour that > at least could be improved. > > Note that the attached VHDL was generated by a HLS tool so it's not easy to > read... and unfortunately I can't reduce the VHDL code to something simpler > that exhibits the slowdown. > > The top-level entity is the testbench entity "tb". The simulation is supposed > to stop after around 550k clock cycles. > > Good evening, > Adrien > _______________________________________________ > Ghdl-discuss mailing list > Ghdl-discuss@gna.org > https://mail.gna.org/listinfo/ghdl-discuss _______________________________________________ Ghdl-discuss mailing list Ghdl-discuss@gna.org https://mail.gna.org/listinfo/ghdl-discuss
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