Hello whygee,
I found a possible reason why VHDL doesn't allow binary operations on
integer here :
http://stackoverflow.com/questions/18365473/bitwise-operations-in-ada :
it seems to be that's because there is variety of ways that a negative
number could be represented, although 2's complement is the most common.
Since VHDL derives from Ada, it must have received the same restrictions
with binary operations, but at least in Ada you could create modulo
integer in which binary operations would be allowed. So in case you
synthetise a code that does binary operations on negative numbers, you
should get different results depending how negative numbers are
represented.
But if there aren't any other good reasons, I also think that binary
operations should be allowed for unsigned integers. For me it makes
sense to be able to define the signed representation of signed numbers
in VHDL and after that I don't see any reason why we couldn't do binary
operation on integers. VHDL is a called an Hardware description
language, so why couldn't we describe how should be represented an
integer ? And other types too, like a FSM ? :
type My_FSM is (Init, Start, Stop) with
Init'Logic => "001", Start'Logic => "010", Stop'Logic => "100";
I mean VHDL isn't like a regular language where you most of the time
don't really care on how things are represented. I believe it needs to
give the user more abilities to describe the representation of the data,
and that without making the language more cumbersome. That's why I'm in
favor of the possibility to define at one place the physical
representation of any types and signals (the low level part) and then
use them without thinking about how they are represented (the high level
part). Exception would be when doing operations that involve the 'Logic
attribute, but it that case, the user works willingly on the low level
part.
Jonas
Le 27. 07. 16 à 00:07, why...@f-cpu.org a écrit :
Le 2016-07-26 20:42, Jonas Baggett a écrit :
Hello,
<snip>
So here are my thoughts about a possible improvement in VHDL. Does it
makes sense for you ?
That's an old and recurring question that several people, including me,
tried to address... without success so far.
There were a few proposals for the VHDL committee but apparently they
died.
For now I use this : http://ygdes.com/GHDL/int_bool/
Greetings,
Jonas
yg
Le 27. 07. 16 à 00:07, why...@f-cpu.org a écrit :
Le 2016-07-26 20:42, Jonas Baggett a écrit :
Hello,
<snip>
So here are my thoughts about a possible improvement in VHDL. Does it
makes sense for you ?
That's an old and recurring question that several people, including me,
tried to address... without success so far.
There were a few proposals for the VHDL committee but apparently they
died.
For now I use this : http://ygdes.com/GHDL/int_bool/
Greetings,
Jonas
yg
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