Hello,
I always had the impression that there must be a better way to handle
numbers than using strings array as numbers as numeric_std does and
creating all the functions needed to do arithmetic on them. I don't know
why the IEEE comity didn't instead decide to allow us to give
specifications on integer types like the size in bits, so that integers
types would be enough for our designs.
So I tryed to imaginate how VHDL could handle numbers in a better way.
Basically there is two changes comparing with normal VHDL :
- use of normal integers for signed/unsigned/fixed point/floated point
numbers but we specify all the needed constraints (size, endianness,
possible logic states like 'X', 'U', 'Z', etc)
- We can specify a number as modulo or not
Here is some pseudo code, which will explain all that better :
----------------------------------------------------------------------------------------
std.vhd (where standard types are defined) :
-- Universal_Unsigned is any natural number between 0 and infinity
subtype Unsigned is Universal_Integer with
Big_Endianness => True,
Logic'Min_LSB => 0,
(…)
-- Std_Logic_Unsigned emulates IEEE.Numeric_Std.Unsigned, so we add some
extra
-- states to the default states that are ('0', '1')
subtype Std_Logic_Unsigned is Unsigned with
Logic'Extra_States => ('U', 'X', 'Z', 'W', 'L', 'H', '-'),
Logic'Reset_State => 'U';
----------------------------------------------------------------------------------------
example_of_use.vhd :
-- Equivalent to Unsigned (7 downto 0) in normal VHDL code :
signal A, B, D : Unsigned with Size => 8;
signal C : Unsigned with Size => A'Size + 1;
signal D : Unsigned with Size => 12;
signal E : Std_Logic_Unsigned with Size => 8;
-- Define a tri-state unsigned subtype by overriding the
Logic'Extra_States
-- attribute of the type Unsigned
subtype Tristate_Unsigned is Unsigned with Logic'Extra_States => ('Z');
signal F : Tristate_Unsigned with Size => E'Size;
signal H : Unsigned with Size 8;
-- I is a modulo unsigned number
signal I : modulo Unsigned with Size => 8;
-- Overrides default endianness for the type Unsigned
signal J : Unsigned with Size => 8, Logic'Big_Endianness => False;
-- Compilation error : lack of a size constraint !
signal Y : Std_Logic_Unsigned;
begin
-- No resize operation needed since A, B and C are not arrays unlike a
-- IEEE.Numeric_Std.Unsigned signal, but an integer subtype
C <= A + B;
-- The 'Logic attribute allows to do binary affectations and
operations on
-- numbers the same way we do in normal VHDL.
-- 'Logic return a character array (just as is a Bit_Vector or a
-- Std_Logic_Vector).
-- For a Unsigned type, possible values are limited to '0', '1'
-- For a Std_Logic_Unsigned, possible values corresponds to all the
-- possible values of a Std_Logic type in normal VHDL.
D'Logic <= (A'Logic OR B'Logic) & C'Logic (0) & "110";
E'Logic <= "101000ZZ";
-- This is legal because Logic_Unsigned is a subtype of Unsigned
E <= A - B
-- This is still legal because the type of Unsigned'Logic is a subset
-- of the type of Logic_Unsigned'Logic, just as e.g. a natural
number is a
-- subset of an integer number
E'Logic <= Not A'Logic;
-- This is also still legal, but an error can be raised during
simulation
-- if E'Logic contains anything other than '0', '1' and 'Z'
F'Logic <= E'Logic;
-- Constraint error in case of an overflow; during compilation a warning
-- will point to a possible overflow with the addition of two 8 bits
-- number which results normally to a 9 bits number
H <= A + B;
-- No constraint error in case of an overflow because J is a modulo
number
I <= A + D;
----------------------------------------------------------------------------------------
And of course signed, fixed point and floated point numbers will be
handled the same way.
Advantages :
+ As long as signal'Logic is only '0' or '1', operations on a number are
fast to simulate because it is only basic binary or integer operations
to do.
+ Leads to cleaner VHDL code because less conversion functions are
needed and we don't do arithmetic operations that mix strings with
numbers anymore. And this without removing the safeties of a strongly
typed language.
+ Overflow bugs on non modulo numbers are easier to catch because a
constraint error will raise.
+ A lot easier to create custom numbers (sub)types with different
specifications (like the Tristate_Unsigned subtype in the example above) :
- Because we don't need to rewrite a library like std_numeric.
- And they are still compatible with the standard numbers types
because they derivate from them.
+ Normally still compatible with numeric_std as long as we avoid name
collisions.
So here are my thoughts about a possible improvement in VHDL. Does it
makes sense for you ?
Greetings,
Jonas
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