> On Nov 12, 2016, at 9:58 AM, Carlos Alberto Ruiz <cr...@dasphotonics.com > <mailto:cr...@dasphotonics.com>> wrote: > > Hello Andrey, > > I've changed the code and made it compatible with standard VHDL. > > ---
Non-static expressions as actuals in port map associations is a -2008 feature. IEEE Std 1076-2008 6.5.6.3 Port clauses para 6: If the actual part of a given association element for a formal port of a block is the reserved word inertial followed by an expression, or is an expression that is not globally static, then the given association element is equivalent to association of the port with an anonymous signal implicitly declared in the declarative region that immediately encloses the block. The signal has the same subtype as the formal port and is the target of an implicit concurrent signal assignment statement of the form anonymous <= E; where E is the expression in the actual part of the given association element. The concurrent signal assignment statement occurs in the same statement part as the block. -- The equivalent section in -2000 (-2002 or earlier) is 1.1.1.2 Ports, where paragraph 4 specifies an expression must be globally static: To communicate with other blocks, the ports of a block can be associated with signals in the environment in which the block is used. Moreover, the ports of a block may be associated with an expression in order to provide these ports with constant driving values; such ports must be of mode in. A port is itself a signal (see 4.3.1.2); thus, a formal port of a block may be associated as an actual with a formal port of an inner block. The port, signal, or expression associated with a given formal port is called the actual corresponding to the formal port (see 4.3.2.2). The actual, if a port or signal, must be denoted by a static name (see 6.1). The actual, if an expression, must be a globally static expression (see 7.4). -- Also note that with the implicit signal you incur a simulation delta cycle delay in the assignment, something to take into account for zero delay modeling. Also see Peter Ashenden and Jim Lewis's book 'VHDL 2008 Just the New Stuff' Chapter 6 Modeling Enhancements, 6.1 Signal Expressions in Port Maps. I don't believe ghdl supports non-static expressions as actual with --std=08 (as yet). I'd dispute it's any more succinct - although brief, not clearly expressed because of the hidden delta cycle delay in the implicitly declared signal assignment. > El 11-11-2016 15:34, Andrey Gursky escribió: > >> Hi Carlos, >> >> On Tue, 25 Oct 2016 16:39:51 +0200 Carlos Alberto Ruiz wrote: >> >>> Thanks for the response Andrey Gursky. >>> >>> I use VHDL 2000. Im having errors in a lot of ports. For example: >>> >>> signal in_0 : std_logic; >>> signal out_0 : std_logic'; >>> >>> signal out_1 : std_logic'; >>> >>> IP0: ip0 port map ( >>> input => in_0 & in_0, -- ERROR >>> output => out_0 >>> ); >>> >>> IP1: ip1 port map ( >>> input => out_0 and out_0, -- ERROR >>> output => out_1 >>> ); >>> >>> I can´t put expression in ports. Is there any way you could do it? I >>> have a really big design and is very tedious change everything. >>> I want to use GHDL with VUNIT, so I would not change compiler. >>
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