SystemVerilog syntax highlighting You can view, comment on, or merge this pull request online at:
https://github.com/geany/geany/pull/1831 -- Commit Summary -- * Create filetypes.SystemVerilog.conf -- File Changes -- A data/filedefs/filetypes.SystemVerilog.conf (65) -- Patch Links -- https://github.com/geany/geany/pull/1831.patch https://github.com/geany/geany/pull/1831.diff -- You are receiving this because you are subscribed to this thread. Reply to this email directly or view it on GitHub: https://github.com/geany/geany/pull/1831
