@cousteaulecommandant Thanks. I think nobody from Geany developers uses Verilog so I guess we'll trust your choices :-).
> I have added all those "new" keywords to the word3= category to distinguish them from the "classic" keywords from the previous century, although I honestly don't know what's the difference between the two categories. I think it would be best to put the new keywords to the "word" list among the original keywords. The only difference is the coloring of the various lists - see the mapping to the theme colors: ``` word=keyword_1 word2=keyword_2 word3=keyword_3 ``` > Finally, I have added $ to the list of wordchars=, because Verilog is special and considers $ to be an identifier character like _ (so e.g. $finish and gotabout$350 are valid identifiers). Note that Geany currently doesn't respect the `wordchars` characters for everything and for some things the "old" hard-coded `a-zA_Z0-9_` is still used. Should be fixed eventually. > (Note that this PR is unrelated to SystemVerilog; all I added here is still plain old Verilog. I still plan to create a commit adding support for SystemVerilog, but that'll be on a different PR.) Just a note - the Verilog ctags parser contains also System Verilog parser. We could enable it if you add the SystemVerilog filetype. > As a side note, I see that words2= includes a bunch system tasks and functions ($display, $finish, etc.), but the list is not complete (see [chapter 17 of the Verilog standard](https://www.eg.bucknell.edu/~csci320/2016-fall/wp-content/uploads/2015/08/verilog-std-1364-2005.pdf#page=307) for a complete list; there are 122 in total). > Do you think it would be a good idea to add those as well? > Note that these are not "keywords" per se, just system functions, but I suppose it's OK to handle them as "keywords" for the purpose of highlighting. (They're highlighted in a different color from actual keywords, which is the important thing.) Depends whether Verilog users would expect them to be highlighted or not. The other "keyword" lists are used this way for other languages too but I don't know what's the common practice for Verilog. -- Reply to this email directly or view it on GitHub: https://github.com/geany/geany/pull/4037#issuecomment-2466468334 You are receiving this because you are subscribed to this thread. Message ID: <geany/geany/pull/4037/[email protected]>
