> (Note that this PR is unrelated to SystemVerilog; all I added here is still plain old Verilog. I still plan to create a commit adding support for SystemVerilog, but that'll be on a different PR.)
There's also this PR you might want to check https://github.com/geany/geany/pull/1831 - if it's alright, maybe that one could be merged. -- Reply to this email directly or view it on GitHub: https://github.com/geany/geany/pull/4037#issuecomment-2466479143 You are receiving this because you are subscribed to this thread. Message ID: <geany/geany/pull/4037/[email protected]>
