I added a few review comments - mostly, since the filetype uses an existing lexer, it doesn't have to be a builtin filetype.
> I understood that tag categories were named mostly for convenience, but apparently the behavior of something marked as tm_tag_variable_t is not the same as that of something marked tm_tag_local_var_t, for example. And now, the problem is that SystemVerilog is not a "programming language" but a hardware description language, so trying to figure out how a "port" or a "module" maps to a set of tags intended for programming is complicated. If this were a matter of "getting creative" and assigning the tags randomly, that'd be done, but apparently I need to be careful because assigning one tag or another will result in different propagation rules, showing up or not on the left panel, etc. There are many other languages that don't fit the "classical programming language" pattern - for them, you can make the assignments almost arbitrarily. Just avoid `tm_tag_local_var_t` which doesn't show symbols in the sidebar. `tm_tag_undef_t` ignores the symbol completely. You also have to specify these in the groups below so they are shon correctly in the sidebar. -- Reply to this email directly or view it on GitHub: https://github.com/geany/geany/pull/4039#issuecomment-2466898594 You are receiving this because you are subscribed to this thread. Message ID: <geany/geany/pull/4039/[email protected]>
