@techee requested changes on this pull request.
I don't know how much finished this PR is but I added a few comments. Also, I'm
not sure if you want to apply some of the changes you made to
https://github.com/geany/geany/pull/4037 to this PR as well.
Finally, a unit test should be added under tests/ctags (check the HACKING file
for more details). The unit test should include some SystemVerilog code that
covers all the kinds except those mapped to `tm_tag_undef_t`.
> @@ -788,6 +788,64 @@ static TMParserMapGroup group_VERILOG[] = {
{N_("Variables"), TM_ICON_VAR, tm_tag_variable_t},
};
+static TMParserMapEntry map_SYSVERILOG[] = {
If the `tm_tag_...` mapping is identical for both Verilog and SystemVerilog, I
think it would be best to define the common part using a macro and reuse the
mapping for both the dialects - see how it's done for C/C++ using the COMMON_C
macro above.
For the comment we use the full kind name (3rd member) defined here
https://github.com/universal-ctags/ctags/blob/dc5edb05845c65c67270a597c4a4e96b08fad2c1/parsers/verilog.c#L175-L207
> @@ -788,6 +788,64 @@ static TMParserMapGroup group_VERILOG[] = {
{N_("Variables"), TM_ICON_VAR, tm_tag_variable_t},
};
+static TMParserMapEntry map_SYSVERILOG[] = {
+ // Verilog and SystemVerilog
Drop this comment.
> + {'M', tm_tag_undef_t},/**/ // modport
+ {'K', tm_tag_package_t}, // package
+ {'P', tm_tag_namespace_t}, // program
+ {'Q', tm_tag_undef_t},/**/ // prototype
+ {'R', tm_tag_undef_t},/**/ // property
+ {'S', tm_tag_struct_t}, // struct
+ {'T', tm_tag_typedef_t}, // typedef
+ {'H', tm_tag_undef_t},/**/ // checker
+ {'L', tm_tag_undef_t},/**/ // clocking
+ {'q', tm_tag_undef_t},/**/ // sequence
+ {'w', tm_tag_member_t}, // member
+ {'l', tm_tag_class_t}, // ifclass (SV equivalent of a Java
interface)
+ {'O', tm_tag_undef_t},/**/ // constraint
+ {'N', tm_tag_undef_t},/**/ // nettype
+
+ // TODO: decide most fitting categories for each
Drop all the TODO comments and the `/**/` comments above.
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