#3557: CPU Vector instructions in GHC.Prim
---------------------------------+------------------------------------------
Reporter: guest | Owner: vivian
Type: feature request | Status: new
Priority: normal | Milestone: _|_
Component: Compiler (NCG) | Version: 6.11
Keywords: | Testcase:
Blockedby: | Difficulty: Unknown
Os: Unknown/Multiple | Blocking:
Architecture: Unknown/Multiple | Failure: None/Unknown
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Comment(by vivian):
Okay, thanks for that point rl. In that case, it seems that what needs
doing is adding packed types to the `Width` type:
{{{
data Width = W8 | W16 | W32 | W64
| W80 -- Extended double-precision float,
-- used in x86 native codegen only.
-- (we use Ord, so it'd better be in this order)
| W128
| W8_16, W16_8, W32_4, W64_2 -- NEW Widths for packed types
-- which fit into XMM 128
registers
deriving (Eq, Ord, Show)
}}}
Which means we can use the current `MachOp`, for example,
{{{
MO_Add W32_4
}}}
will use SSE registers to add 4 packed i32's.
With respect to the XMM registers (8 or 16 depending upon CPU), upon which
the SSE instructions operate, should a new type be added to `GlobalReg`
{{{
data GlobalReg
-- Argument and return registers
= VanillaReg -- pointers, unboxed ints and chars
{-# UNPACK #-} !Int -- its number
VGcPtr
| FloatReg -- single-precision floating-point registers
{-# UNPACK #-} !Int -- its number
| DoubleReg -- double-precision floating-point registers
{-# UNPACK #-} !Int -- its number
| LongReg -- long int registers (64-bit, really)
{-# UNPACK #-} !Int -- its number
| XmmReg -- 128 bit xmm registers
{-# UNPACK #-} !Int -- its number
}}}
or should this be left to the backend, since it is target-specific whether
an SSE intrinsic can be used?
--
Ticket URL: <http://hackage.haskell.org/trac/ghc/ticket/3557#comment:11>
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