Hi, === Conditional compilation ===
On 28 October 2010 22:21, GHC <[email protected]> wrote: > #3557: CPU Vector instructions in GHC.PrimComment(by vivian): > > | W8_16, W16_8, W32_4, W64_2 -- NEW Widths for packed types > -- which fit into XMM 128 > > If we add these new datatypes to Cmm, take an instruction: > MO_F_Add W32_4 > > > -- in StgCmmPrim.hs > translateOp Float4AddOp = Just (MO_F_Add W32_4) so the new Haskell primitive is `Float4AddOp#`. What do we do on architectures that don't support this operation natively? To replace it with an assembler routine that adds two vectors of 4 Floats defeats the purpose stated by rl that we want to do complex operations on each data unit (e.g. xmm128). Do we conditionally compile primops and thus not worry in Cmm about architectures that don't support SSE instructions? === New operations === There are now CPU primitives reciprocal and dot product for the SSE packed types. Do we add these as `MachOp`s or `CallishMachOps`? === Memory Operations === There are new operations for streaming applications that bypass the cache. If we have a Haskell `Vector (Float,Float)` representing a stereo audio stream and we want to process each element, then what we'd like is the CPU to FETCH xmm1 xmm2 XMM_OP1 xmm1 xmm2 ... ... 'complex operations on each W32_4 unit ... XMM_OPN STORE xmm1 xmm2 Where FETCH and STORE are the new no-cache streaming operations and each data unit is manipulated in some complex way. With stream fusion this seems relatively simple (from the Haskell end), except that we now need to be able to figure out when to using streaming memory operations, but we're adding the other XMM ops as singletons. Do we need some sort of vector/stream datatype in Cmm? === compiler flags === Is it possible to add #define TARGET_CPU_SSE #define TARGET_CPU_SSE2 #define TARGET_CPU_SSE3 #define TARGET_CPU_SSE4 #define TARGET_CPU_SSE5 to the ghc build process and ghc? These have been adopted by a number of chip-makers. === Numeric constants === Some CPUs provide hardwired numerical constants (pi, ln2,...), do we want to provide machine ops for these? Thanks for your time. Vivian
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