#3557: CPU Vector instructions in GHC.Prim
---------------------------------+------------------------------------------
Reporter: guest | Owner: vivian
Type: feature request | Status: new
Priority: normal | Milestone: _|_
Component: Compiler (NCG) | Version: 6.11
Keywords: | Testcase:
Blockedby: | Difficulty: Unknown
Os: Unknown/Multiple | Blocking:
Architecture: Unknown/Multiple | Failure: None/Unknown
---------------------------------+------------------------------------------
Comment(by guest):
Replying to [comment:25 rl]:
> FWIW, I don't think those reasons are entirely correct. I would suggest
moving the page back. Vector instructions ''are'' SIMD instuctions. Vector
computing is, to me, something fairly different. The relevant Wikipedia
pages have a lot of information which might help clear up the confusion.
I do not know what Wikipedia pages are relevant for you, but I think
http://en.wikipedia.org/wiki/Vector_processor
supports the view, that SSE and AltiVec are about vector computing (or
vector processing) not about parallel/SIMD computing. The same applies to
the Blog article that compares Larrabee with NVidia GPUs.
I do not see a reason to throw together two different approaches. Do we
disagree on the naming or on the statement, that there are two different
approaches to tackle repetitive computations?
--
Ticket URL: <http://hackage.haskell.org/trac/ghc/ticket/3557#comment:26>
GHC <http://www.haskell.org/ghc/>
The Glasgow Haskell Compiler
_______________________________________________
Glasgow-haskell-bugs mailing list
[email protected]
http://www.haskell.org/mailman/listinfo/glasgow-haskell-bugs
