On 2016-12-02 12:18:25 +0100, Wolf Lammen wrote: > Gesendet: Freitag, 02. Dezember 2016 um 01:30 Uhr > Von: "Vincent Lefevre" <[email protected]> > An: "Nelson H. F. Beebe" <[email protected]> > Cc: [email protected] > Betreff: Re: Help stabilising mini-gmp [...] > > I'm not talking about a zero shift count, but a shift of the value 0 > > with an arbitrary shift count, e.g. (uint64_t) 0 << 64. This is > > undefined behavior, but I wonder why. When mapped to a hardware > > instruction, does the result depend on the platform? > > I wonder whether the possibly multiple encodings of 0 is the reason. > We are used to two's complement encoding of integers, but the C/C++ > standard allows other (from the today's point of view exotic) > encodings like for example one's complement. And here 0 can have the > encoding all bits clear or all bits set. Now left shift FFFFFFFF ...
No, this is not the reason. For instance, 0 << 1 is well-defined and the result is 0. So, on such a processor, the compiler would have to make sure that 0 is represented as a positive 0 (all bits clear) before the hardware shift is done. Then the fact that this should work with valid shift counts implies that this will still work with out-of-range shift counts: the register with all bits clear will always give a value with all bits clear, whatever the shift count. -- Vincent Lefèvre <[email protected]> - Web: <https://www.vinc17.net/> 100% accessible validated (X)HTML - Blog: <https://www.vinc17.net/blog/> Work: CR INRIA - computer arithmetic / AriC project (LIP, ENS-Lyon) _______________________________________________ gmp-devel mailing list [email protected] https://gmplib.org/mailman/listinfo/gmp-devel
