Hi Al. to my surprise (in 0.36), this gnucap> verilog gnucap-verilog>capacitor #(.c(1)) resistor (.p(1),.n(2)); gnucap-verilog>resistor r (1,2); gnucap-verilog>list
results in capacitor #(.c(1)) resistor (.p(1),.n(2)); capacitor #(.c(1)) r (.p(1),.n(2)); a similar collision happened while parsing one of my geda schematics (also using LANGUAGE::find_proto), which is bad. i have no idea what to do, in case this is not a bug... regards felix _______________________________________________ Gnucap-devel mailing list [email protected] https://lists.gnu.org/mailman/listinfo/gnucap-devel
