On Thu, Jan 17, 2013 at 03:23:54PM -0500, al davis wrote: > First, lets assume that the following is correct. (is it?) > > gnucap> verilog > gnucap-verilog>bogus r (1,2); > bogus r (1,2); > ^ ? bogus: no match > gnucap-verilog>list > gnucap-verilog> > > I believe this is correct because there is no type "bogus", and > gnucap is correctly rejecting it.
thats what iverilog would do. "<filename>:<linenumber>: error: Unknown module type: bogus" don't know what the standard says. > Now, try this ..... > > gnucap> verilog > gnucap-verilog>capacitor #(.c(1)) bogus (.p(1),.n(2)); > gnucap-verilog>bogus r (1,2); > gnucap-verilog>list > capacitor #(.c(1)) bogus (.p(1),.n(2)); > capacitor #(.c(1)) r (.p(1),.n(2)); > gnucap-verilog> > > In this case, the capacitor's name is "bogus". The next line > declares another instance "r", which is a clone of bogus. > > The question .... > > Should the line beginning with "bogus" be rejected or not? iverilog does reject it. > Does the Verilog spec say what is expected when there are > duplicate labels? missing labels? i don't know. but is this a verilog issue? potentially some or other language plugin might want to (dis)allow bogus declarations, so find_looking_out should make it optional. i think, optionally just returning cards if !is_device(), would at least solve my problem. thanks felix _______________________________________________ Gnucap-devel mailing list [email protected] https://lists.gnu.org/mailman/listinfo/gnucap-devel
