On 05/27/2013 01:32 AM, al davis wrote:
On Monday 27 May 2013, Felix Salfelder wrote:
>lets
>draw a clear line between user and developer.
The line isn't so clear. A "user" could be using Verilog-AMS as
a simulation language. The behavioral models need to be
compiled. So, "users" are making plugins.
Yes, and users in chip design often write verilog models and such,
and I want translation to happen and would like to be able to
help more without being a C++ expert, but if needed to get some
netlist translation
to work, it should be possible. Seems like a grey area between
users/developers.
John Griessen
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