guix_mirror_bot pushed a commit to branch master
in repository guix.
commit 011f0580bea97783d3d76d85af8d42b887462355
Author: Cayetano Santos <[email protected]>
AuthorDate: Thu Aug 14 16:43:55 2025 +0200
gnu: Add apycula.
* gnu/packages/electronics.scm (apycula): New variable.
Change-Id: Iba09d271baedc84a8087275aed4d4cc32dccc8d9
Signed-off-by: Maxim Cournoyer <[email protected]>
Modified-by: Maxim Cournoyer <[email protected]>
---
gnu/packages/fpga.scm | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 0ff3025187..4a8c535a6f 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -144,6 +144,29 @@ formal verification.")
formal verification. This is the Yosyshq fork of ABC.")
(license (license:non-copyleft "file:///copyright.txt"))))
+(define-public apycula
+ (package
+ (name "apycula")
+ (version "0.22")
+ ;; The pypi tar.gz file includes the necessary .pickle files, not available
+ ;; in the home-page repository.
+ (source
+ (origin
+ (method url-fetch)
+ (uri (pypi-uri "Apycula" version))
+ (sha256
+ (base32 "15xwmi6z2p7jz17l5bqs511yh8jis1dacqc8fypx49jysl7h0apd"))))
+ (build-system pyproject-build-system)
+ (arguments (list #:tests? #f)) ;requires Gowin EDA tools
+ (inputs (list python-crc))
+ (native-inputs (list python-setuptools python-wheel))
+ (home-page "https://github.com/YosysHQ/apicula/";)
+ (synopsis "Gowin FPGA bitstream format")
+ (description
+ "The project Apycula provides tools to support development and
+generating bitstreams with Gowin FPGAs.")
+ (license license:expat)))
+
(define-public iverilog
(package
(name "iverilog")
