guix_mirror_bot pushed a commit to branch master
in repository guix.
commit 3d55f5c6b96fb237e7114422bffc4de0c8182e24
Author: Cayetano Santos <[email protected]>
AuthorDate: Tue Aug 26 17:46:39 2025 +0200
gnu: verilator: Improve style.
* gnu/packages/fpga.scm (verilator)[arguments]: Use G-Expressions.
Change-Id: I3c04b4a632baaa8f2ff2f79354954fccafbbfd4a
Signed-off-by: Ludovic Courtès <[email protected]>
---
gnu/packages/fpga.scm | 42 ++++++++++++++++++++++--------------------
1 file changed, 22 insertions(+), 20 deletions(-)
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 0556d1fafb..e12bd6dce4 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -795,29 +795,31 @@ using different abstraction levels.")
(list perl python systemc))
(build-system gnu-build-system)
(arguments
- '(#:phases
- (modify-phases %standard-phases
- (replace 'bootstrap
- (lambda _ (invoke "autoconf")))
- (add-after 'unpack 'adjust-source
- (lambda _
- (substitute* "bin/verilator"
- (("/bin/echo") "echo"))))
- (add-before 'check 'disable-gdb-safe-path
- (lambda _
- (setenv "HOME" (getcwd))
- (mkdir-p (string-append (getcwd) "/.config/gdb"))
- (with-output-to-file (string-append (getcwd)
"/.config/gdb/gdbinit")
- (lambda ()
- (display "set auto-load safe-path /"))))))
- #:test-target "test"))
+ (list
+ #:phases
+ #~(modify-phases %standard-phases
+ (replace 'bootstrap
+ (lambda _ (invoke "autoconf")))
+ (add-after 'unpack 'adjust-source
+ (lambda _
+ (substitute* "bin/verilator"
+ (("/bin/echo") "echo"))))
+ (add-before 'check 'disable-gdb-safe-path
+ (lambda _
+ (setenv "HOME" (getcwd))
+ (mkdir-p (string-append (getcwd) "/.config/gdb"))
+ (with-output-to-file
+ (string-append (getcwd) "/.config/gdb/gdbinit")
+ (lambda ()
+ (display "set auto-load safe-path /"))))))
+ #:test-target "test"))
(home-page "https://www.veripool.org/verilator/";)
(synopsis "Verilog/SystemVerilog simulator")
(description
- "Verilator transforms the specified Verilog or SystemVerilog code by
reading it,
-performing lint checks, and optionally inserting assertion checks and
-coverage-analysis points. It outputs single- or multi-threaded @file{.cpp}
-and @file{.h} files.")
+ "Verilator transforms the specified Verilog or SystemVerilog code by
+reading it, performing lint checks, and optionally inserting assertion checks
+and coverage-analysis points. It outputs single- or multi-threaded
+@file{.cpp} and @file{.h} files.")
(license license:lgpl3)))
(define-public fftgen
