There is no 'later' P-M core than Yonah
On 2 Dec 2005, at 02:25:230, Greg Sevart wrote:
Um Hayes, they are doing that.
reference: Merom, Conroe, Woodcrest
64bit 65nm chips due in the middle of '06, 14 stage pipelines,
2-3Ghz clocks, 4-issue dispatch! (A64s are 3 issue, G5s are 3
+branch, P4's are 2-issue)
Pentium M is P3 derived, and lacks the 64bitness, rather that
futz around giving it a 64bit overhaul, they're designing
something based on a similar philosophy from the ground up..
Yes, but Yonah and later PM cores have an extra 4-cycle latency on
the L2 cache. Hopefully, this can be disabled at will....it comes
from the core's ability to shut down cache areas that aren't needed
and flush contents to memory.
This does necessarily hurt the performance per MHz, but it is still
very competitive.
Greg
There is no 'later' P-M core than Yonah, Merom/Conroe/Woodcrest are
ground up designs built around a performance/watt approach, hopefully
they realise that they were on to a good thing with Prescotts branch
predictor though. (seriously, that it keeps up with Northwood EVER is
testament to that.)
I believe some of the hit on Yonahs L2 latency is because it's a
shared L2 between both cores though, I thought Dothan and Banias
could already shut down L2 on an area of associativity basis also?
-_-_
James Boswell
[EMAIL PROTECTED]
ICQ : 1653327 | AIM : TorazChryx
MSN: [EMAIL PROTECTED]
