On 14/03/12 02:51, Alexander Graf wrote:
But I thought that the QEMU order was the reverse as given in the
specification? For example, on p.735 describing the MSR, the SF (Sixty Four)
bit flag is described as bit 0, where as in target-ppc/cpu.h MSR_SF is given as
63.
Yes, exactly :). So if the spec says that bits 33-36 and 42-47 are loaded with
interrupt specific information, these fall into the lower 32 bits.
In QEMU, we use the typical C notion where the LSB is 0. That makes it
confusing to understand what's going on at times, as all the numbers diverge
from the spec. But that's life.
In fact, because it's so utterly confusing, I wrote myself this small C program
a while ago which makes it a lot easier to compare numbers between the 2
notations:
#include<stdio.h>
int main(int argc, char **argv)
{
unsigned long long value = 0, length = 0, i;
if(argc != 3) return 1;
value = strtoull(argv[1], 0, 0);
length = strtoull(argv[2], 0, 0);
printf("Value: %#llx\n\n", value);
printf("64 32 le\n");
printf("--------\n\n");
for(i=0; i<length; i++) {
printf("%02d %02d %02d: %s\n", 63-i, 31-i, i,
(value& (1ULL<< i)) ? "x" : "");
}
}
Ha okay - I've obviously confused myself with the endian swap in QEMU :/
Let me make some changes, re-test and see if it's possible to submit a
corrected patch that will still work with all of my test images.
ATB,
Mark.
_______________________________________________
HelenOS-devel mailing list
[email protected]
http://lists.modry.cz/cgi-bin/listinfo/helenos-devel
