On 5.4.2012 14:54, Jiri Svoboda wrote: >> Moreover, all accesses to the structure must be done using the >> pio_read/write_n() functions so the proper access width is >> guaranteed. > Yes but at least on some arches these functions are written in C and > they're inline. GCC will propagate the information about the packed > nature of the structure all the way to the core of the function (no, > really!) and generate a non-atomic access. Believe me, I found out > the hard way (on ARM when porting to the FreeRunner).
Well, I do remember the annecdote with FreeRunner, but then, have you used ioportN_t as domain types for the register struct members? Looking on e.g. the FreeRunner UART registers from the Camp of 2010 suggests the opposite, but I might be still missing something. I would like to test this on a simple example. I also remember when using volatile in case of programming the APIC prevented the compiler from turning accesses to 32-bit IO registers into a series of 8-bit accesses. Anyway, I am going to make myself a small SPARC sample and see... Jakub _______________________________________________ HelenOS-devel mailing list [email protected] http://lists.modry.cz/cgi-bin/listinfo/helenos-devel
