Hallo, I am interested in using Verilog-A files with gnucap. If this is still not possible I would like to make something (proof-of-concept at first, probably with Icarus Verilog as compiler).
On gnucap-wiki-homepage site is written "You can also use the "ADMS" model compiler, to generate a Spice model, ...", but I haven't found either any working example nor any *.c-file on the ADMS-homepage. Also on the same wiki-page is written "There is work in progress to use Icarus Verilog as the [Verilog?] model compiler." Does somebody know if one of these two projects is really working and if "Icarus Verilog Code Generator"-like-project would be still useful? Thanks in advance, Andreas _______________________________________________ Help-gnucap mailing list [email protected] http://lists.gnu.org/mailman/listinfo/help-gnucap
