On Tue, Feb 03, 2015 at 09:37:27AM +0000, Manthe Thomas - Maschinenfabrik 
Reinhausen wrote:
> Ist es generell nicht vorgesehen, ein Verilog-A-Modul in SPICE
> aufzurufen oder sollte dies funktionieren und ich habe nur einen
> Syntaxfehler in meiner Datei?

[from german:
 i'd like to instanciate a Verilog-A module as a SPICE subckt, using the
 letter X. is this possible?
]

Hi there.

this is a valid question. spectre allows something like

.ahdl_include something.va
Xmysomething a b c something width=19.

gnucap-adms does not provide subckt style instanciable components. maybe
it could, i think spice is obsolete enough, so i did not bother. for
now, use the verilog style netlister. also, there is a hack that might
make
.something mys a b c width=19
work in spice mode. haven't tried for a while.

don't hesitate to send me a patch, if you have one.

cheers
felix

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