I posted an email last week, but I've not received any answer. Perhaps I wasn't able to explain my problem clearly; I'll try again.
I need to write a makefile that allows me to build from basically the same sources two different targets. The first is an application (.exe file I mean), the latter is a library (.so module). The rules for both the target are nearly the same, only some compiler options change.
My intention was to write something like this:
.PHONY: foo
foo: app.exe
app.exe: $(fooObjectFiles) $(CCompiler) $(fooCFLAGS) $(fooLDFLAGS) $^ -o $@
%.o: %.c $(CCompiler) $(fooCFLAGS) -c $^ -o $@
.PHONY: bar
bar: lib.so
lib.so: $(barObjectFiles) $(CCompiler) $(barCFLAGS) $(barLDFLAGS) $^ -o $@
%.o: %.c $(CCompiler) $(barCFLAGS) -c $^ -o $@
and call make in the following way:
% make foo // When I want to build app.exe
% make bar // When I want to build lib.so
However it doesn't work, because of the double %.o: %.c rule. How can I force make to execute the rule related to the target that I want to build?
Thanks in advance, Andrea.
--- Andrea Riciputi
"Science is like sex: sometimes something useful comes out, but that is not the reason we are doing it" -- (Richard Feynman)
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