This is reasonably familiar and can be cleared up by providing 1 "%.o: %.c"
rule rather than 2:
%.o: %.c
$(CCompiler) $(CFLAGS) -c $^ -o $@
Then determining the CFLAGS based on the target that make is invoked with.
The target is usually defined in $(MAKECMDGOALS) so the following would work
with your examples (if placed before the rules):
ifeq (bar,$(filter bar, $(MAKECMDGOALS)))
CFLAGS = $(barCFLAGS)
else
CFLAGS = $(fooCFLAGS)
endif
Similar can be done for the LDFLAGS...
Another (and perhaps better) way of doing the same thing is to split the
rules for each item into separate makefiles and keep the common items in an
included file:
makefile.app
> include makefile.common
> .PHONY: foo
>
> foo: app.exe
>
> app.exe: $(ObjectFiles)
> $(CCompiler) $(fooCFLAGS) $(fooLDFLAGS) $^ -o $@
>
> %.o: %.c
> $(CCompiler) $(fooCFLAGS) -c $^ -o $@
>
makefile.lib
> include makefile.common
> .PHONY: bar
>
> bar: lib.so
>
> lib.so: $(ObjectFiles)
> $(CCompiler) $(barCFLAGS) $(barLDFLAGS) $^ -o $@
>
> %.o: %.c
> $(CCompiler) $(barCFLAGS) -c $^ -o $@
>
makefile.common
> ObjectFiles = x.o y.o ....
>
This isn't perfect, but hopefully you get the ideal. Splitting makefiles up
allows better maintenance in some ways because you modularise - and just as
in software, you could reuse modules!
Regards,
B.
-----Original Message-----
From: Andrea Riciputi [mailto:[EMAIL PROTECTED]
Sent: 25 February 2003 15:18
To: Make Help
Subject: Make-ing different build.
Hi,
I posted an email last week, but I've not received any answer. Perhaps
I wasn't able to explain my problem clearly; I'll try again.
I need to write a makefile that allows me to build from basically the
same sources two different targets. The first is an application (.exe
file I mean), the latter is a library (.so module). The rules for both
the target are nearly the same, only some compiler options change.
My intention was to write something like this:
> .PHONY: foo
>
> foo: app.exe
>
> app.exe: $(fooObjectFiles)
> $(CCompiler) $(fooCFLAGS) $(fooLDFLAGS) $^ -o $@
>
> %.o: %.c
> $(CCompiler) $(fooCFLAGS) -c $^ -o $@
>
> .PHONY: bar
>
> bar: lib.so
>
> lib.so: $(barObjectFiles)
> $(CCompiler) $(barCFLAGS) $(barLDFLAGS) $^ -o $@
>
> %.o: %.c
> $(CCompiler) $(barCFLAGS) -c $^ -o $@
>
and call make in the following way:
% make foo // When I want to build app.exe
% make bar // When I want to build lib.so
However it doesn't work, because of the double %.o: %.c rule. How can I
force make to execute the rule related to the target that I want to
build?
Thanks in advance,
Andrea.
---
Andrea Riciputi
"Science is like sex: sometimes something useful comes out,
but that is not the reason we are doing it" -- (Richard Feynman)
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