Use MAKECMDGOALS. Also, you might be interested in reading: http://aegis.sourceforge.net/auug97.pdf
HTH, Noel S�bastien Hinderer wrote: > > Dear all, > > I would like to write a Makefile which would essentially call other > Makefiles and pass them the target it received on the command-line. > > For instance if there are two subdirectories d1 and d2, and if I enter the > command : > $ make targetxyz > > the following commands should be called : > > make -C d1 targetxyz > make -C d2 targetxyz > > The problem is that the number of targets that will have to be processed > this way is big. So, I would like to avoid something like : > > target1 : > make -C d1 target1 > make -C d2 target1 > > target2 : > make -C d1 target2 > make -C d2 target2 > > target3 : > make -C d1 target3 > make -C d2 target3 > > etc. > > Rather, I would like to have a general rule matching all targets (except, > say, clean and distclean which would be processed in an other way), and > transmitting the target recursively. > > If someone knows how this can be achieved, I'd really appreciate your > help. > By the way, please don't blame me for not having read the maouals. I read > them. Maybe not carefully enough, sorry. > > Best wishes, > S�bastien. > > _______________________________________________ > Help-make mailing list > [EMAIL PROTECTED] > http://mail.gnu.org/mailman/listinfo/help-make _______________________________________________ Help-make mailing list [EMAIL PROTECTED] http://mail.gnu.org/mailman/listinfo/help-make
