On 4/1/06, Tom Bachmann <[EMAIL PROTECTED]> wrote: > ther is a more serious problem I did not see, yet: while the example > makefile is obviously stupid, a real makefile includes another file > between the two assignments, so a more complete definition of foo would be > > define FOO > CFLAGS := foo bar baz foo2 > include OTHERFILE > $(eval $(call SET,CFLAGS)) > endef > > now it begins to make sense (to me), as OTHERFILE can make assignments > like CFLAGS += -DFOO etc. It would be very annoying to always have to > write $(eval ...).
No need. Just put the 'include' in FOO inside an $(eval): ----- define SET $$(NAME)_$(1) := $$($(1)) endef define FOO $(eval CFLAGS := foo bar baz foo2 $(call SET,CFLAGS)) endef $(call FOO,foo/bar) ---- (I realized after replying before that FOO only needs a single $(eval)) > What still confuses me is the following: I can write the initial > sequence and everything works fine, so how can I just transform it into > a "funtion"? By putting the entire body of FOO inside an $(eval) You later wrote: >this seems to work and I guess I understand why it does, but I'm still >wondering if the second parameter for set can be avoided. You need $(NAME) to be expanded in a context where $1 is set to the argument to FOO. That can only be done inside FOO itself. So it either needs to appear textually in FOO (such as in a second argument to SET) or be expanded with $(eval) inside FOO, as seen above. Philip Guenther _______________________________________________ Help-make mailing list [email protected] http://lists.gnu.org/mailman/listinfo/help-make
