Short story: "make test1" executes rules twice, why? "make test2" works
as expected.
Long story: I'm trying to have a generic Makefile that detects platform
using uname and then forwards goals to another Makefile.b. But I am
getting targets being built multiple times. This happens when the target
Makefile.b calls $(MAKE). Currently these $(MAKE) commands do not
specify makefile, and I'd like to keep it that way. So they go to the
default Makefile after which they come back to Makefile.b. But why do
rules get executed twice?
# Makefile
.DEFAULT:
$(MAKE) -f Makefile.b $(MAKECMDGOALS)
# Makefile.b
test1:
$(MAKE) foo bar
test2:
$(MAKE) -f Makefile.b foo bar
foo:
@echo foo
bar:
@echo bar
--
timo
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