> Vincent De Groote <[email protected]>
> I have already tried the rule $(OBJECTS_DIR)/%.o : $(SOURCES_DIR)/%.c
> makefile
>
> but this also doesn't work: it gives the sames results
>
>
> Any other idea ?
>
> Vincent De Groote
>
This is *very* interesting to me but I don't have the answer. I have only
made this sort of work by resorting to a static pattern rule where the
targets are all explicitly named:
# (typed from memory...)
CSRCS = foo.c bar.c
OBJS = $(addprefix, $(OBJDIR), $(CSRCS:.c=.o))
$(OBJS): %.o: %.c
$(CC) -c $(CFLAGS) $< -o $@
But what I'd rather have is an implicit rule (the targets aren't explicit)
with a "build dir" path. I don't if it can be done...
Chris
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