Hi all,
On a project, I have many folders (including makefiles) to compile in a
parallel, and some have some dependencies on others.
For example :
/Makefile
/toto1/Makefile (has dependency on toto2)
/toto2/Makefile
My root Makefile is this one :
DIRS = toto1 toto2
.PHONY: $(DIRS) all clean
all: $(DIRS)
$(DIRS):
@echo DIRS = $(DIRS)
@$(MAKE) -s -C $@
I really need a clean way to explain this root Makefile how dependencies are
made.
I found something that works, but including a rule in toto1/Makefile that
call explicitely toto2/Makefile, but it causes recursive compilation.
So it’s not what I can call a clean way to solve this issue …
Does anyone has some ideas on this subject ?
Regards,
Alexandre.
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