Hi,
The variable assigned in the parent makefile will be carried on to the
child makefile. I'm wondering if there is a way to localize this
effect only to the parent.
$ cat Makefile
.PHONY: all
XX:=abc
$(info $(XX))
all:
$(MAKE) -C dir
$ cat dir/Makefile
.PHONY: all
XX:=abc
$(info $(XX))
all:
$ make XX=100
100
make -C dir
100
make[1]: Entering directory `/tmp/cmdl_arg/dir'
make[1]: Nothing to be done for `all'.
make[1]: Leaving directory `/tmp/cmdl_arg/dir'
--
Regards,
Peng
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