>Hi, > >The variable assigned in the parent makefile will be carried on to the >child makefile. I'm wondering if there is a way to localize this >effect only to the parent. > >$ cat Makefile >.PHONY: all > >XX:=abc > >$(info $(XX)) > >all: > $(MAKE) -C dir > >$ cat dir/Makefile >.PHONY: all > >XX:=abc > >$(info $(XX)) > >all: > >$ make XX=100 >100 >make -C dir >100 >make[1]: Entering directory `/tmp/cmdl_arg/dir' >make[1]: Nothing to be done for `all'. >make[1]: Leaving directory `/tmp/cmdl_arg/dir'
Another alternative to using the 'override' directive is to specify a file on
the command line, and use that file to define variables through the include
feature.
---config.mi---
XX:=xyz
---Makefile---
.PHONY: all
# default
XX:=abc
ifeq ($(origin config-file),command line)
include $(config-file)
endif
$(info $(XX))
all:
$(MAKE) -C dir
---dir/Makefile---
.PHONY: all
XX:=123
$(info $(XX))
all:
$ make config-file=config.mi
It provides a bit more granularity that might be useful in your scenario. You
might have to play with the placement of the inclusion guards and $(origin)
tests to get the exact semantics that you want.
Hope it helps,
John D.
<<winmail.dat>>
_______________________________________________ Help-make mailing list [email protected] https://lists.gnu.org/mailman/listinfo/help-make
