On 2012-11-05, Miguel Guedes wrote: > Hello List! > > > Is it possible to set dependencies in variables and then have GNU Make expand > these dependencies? For instance, let's say we have a project that builds two > binaries, foo and bar. Each of foo and bar have their own dependencies as > defined below: > > > BINARIES := foo bar > > FOO_OBJECTS := foo_obj_1 foo_obj_2 > BAR_OBJECTS := bar_obj_1 bar_obj_2 > > > Now, how would one setup a generic Makefile such that for each target defined > in $(BINARIES) the dependencies $($<_OBJECTS) are added automatically? Perhaps > I'm being too ambitious and this isn't possible at all? > > I've read up on the .SECONDEXPANSION special rule but I don't think that would > allow for what I'm after. > Seems that not possible directly.
Exactly your question resolved by Automake. Just read (search for 'bin_PROGRAMS' keyword): $ info automake $ info autobook But you can automatically generate and include makefiles that perform action you want (I don't test code, debug it yourself): BINARIES_MK := $(patsubst %,%.mk,$(BINARIES_MK)) include $(BINARIES_MK) %.mk: <TAB>@echo '$*: $$($*_OBJECTS)' <TAB>@echo '<TAB>gcc -o $@ $^' Just read: $ info make to get knowledge about 'include' keyword and GNU Make escaping syntax. Also you can add dependency on main makefile to auto-rebuild included makefiles: $(BINARIES_MK): $(firstword $(MAKEFILE_LIST)) Hope this help! -- Best regards! _______________________________________________ Help-make mailing list [email protected] https://lists.gnu.org/mailman/listinfo/help-make
