Hi,
I'm sure this has been asked about before, but I've been attempting to
understand this and failing for a while now.
If I have a project containing a folder hierarchy, which contains a
bunch of source files (mixed c and assembler)
how do I write a set of rules to build the files?
I'd expected this to be a couple of lines of Makefile, but it doesn't
seem that I'm that lucky.
I suspect that my initial approach with a single Makefile at top level
is not going to work, but I don't understand why. I certainly can't get
it to work.
So presumably the "right" approach is to use submakefiles somehow, but
that brings a whole slew of questions about what is defined where, and
what applies to what, and I'm just finding myself completely lost - for
example -
I tried to make a rule that would work for objects located in
subfolders. This is the closest I got, and it worked fine:
$(OBJS): %.o: %.c
mkdir -p .deps/$(@D)
$(CC) $(CFLAGS) -c -o $@ $<
Right up until I added this rule to build the assembler files:
$(OBJS): %.o: %.s
mkdir -p .deps/$(@D)
$(CC) $(ASFLAGS) -c -o $@ $<
Now it tries to find a .s file in order to build an object, even if a
perfectly good .c file exists.
I can swap the order of these rules, and it makes no difference.
indeed, I'm finding it hard to understand the placement of anything in a
makefile - they seem to be processed from top to bottom, but "not
always", and its not obvious how.
I'd also like to know if there's a reliable way to disable all the
"build in" rules and variables, so that I have no risk of "tripping
over" them - I've found -r and -R, but I've also found dire warnings in
(eg. Linux) that this isn't reliable in all versions of make.
Can someone make me a lot less lost?
-Ian
