> 400 MHz Front Side Bus > 128K Cache those two factors above are what makes celerons particuarly bad at serving HLDS/SRDS. The bus speed is a significant bottleneck, especially when the miniscule cache needs to be refilled often.
Much older generation P4 with 400/256k were also poor servers despite their apparent high clockspeeds as they are heavily handicapped by low bus speeds and deep pipelines making small caches inefficient to the point of uselessness. You should get 1x12 pretty happily, 2x12 maybe, and any larger is a matter for experimentation. Matt _______________________________________________ To unsubscribe, edit your list preferences, or view the list archives, please visit: http://list.valvesoftware.com/mailman/listinfo/hlds_linux
